1. Field of the Invention
The present invention relates to a dynamic semiconductor memory device, and more particularly to a dynamic semiconductor multi-value memory device which can rapidly operate.
2. Description of the Prior Knowledge
While the operation speed of a dynamic semiconductor memory device has been remarkably improved, a dynamic semiconductor multi-value memory device remains to operate slower than a two-value dynamic semiconductor memory device, and has a less read-out margin.
FIGS. 5A and 5B illustrate a dynamic semiconductor multi-value memory device which is disclosed in copending U.S. patent application Ser. No. 455,989 commonly assigned and filed on Dec. 22, 1989 and now abandoned. The multi-value memory device of FIGS. 5A and 5B comprises a plurality of four-level memory cells 10, and two sense amplifiers 16 and 17. Each of the four-level memory cells 10 consists of a storage capacitor 11, and two transfer gates 12 and 13. The sense amplifiers 16 and 17 are constructed in the same manner as a sense amplifier used in a conventional two-value memory device.
In this memory device, when the sense amplifiers 16 and 17 are operated to sense the data stored in the four-level memory cells 10, the reference level is determined by capacitors provided in a read-out circuit 28. This requires that during the operation of the sense amplifiers 16 and 17 the capacitors must be charged in response to signals UP1 and UP2, resulting in a problem in that the commencement of the operation of the sense amplifiers 16 and 17 is delayed by the rising period of the signals UPI and UP2.
Furthermore, in the multi-value memory device of FIGS. 5A and 5B, transistors are used to select the capacitors to be charged in the read-out circuit 28. Therefore, the read-out margin of the memory device is restricted by the variation in the threshold value of the transistors in the read-out circuit 28.